The present invention relates to a memory device and to a method of performing a write operation in such a memory device.
When performing write operations in modern memory devices, it is becoming more and more common to use write assist mechanisms in order to improve the writeability of the memory cells being written to. Many of the known write assist techniques involve applying boost voltages either greater than the normal supply voltage, or below the normal ground voltage. One particular approach is the negative bitline boost (NBLB) approach, which is typically a capacitive based approach, and is regarded as one of the most effective ways of boosting writeability of a memory cell.
In modern memory devices, it is also common to use a different voltage supply for the memory cells within the memory array than the voltage supply that is used for much of the associated access circuitry used to perform write operations and read operations within the memory cells of the memory array. In particular, the memory cells of the memory array may be powered by a cell voltage supply (VDDCE), whilst much of the remaining access circuitry is operated from a peripheral voltage supply (VDDPE). By taking such an approach, it is possible to save significant power, since for example the peripheral voltage supply can be turned off whilst the memory is in a retention state. In order to reduce leakage current, it is desirable to place much of the access logic within the peripheral voltage domain, and accordingly it is common for the components used to implement the write assist mechanism to be operated from the peripheral voltage domain.
It is typically the case that when high performance is not required, the peripheral voltage supply can be reduced to a level below that of the cell voltage supply, thereby enabling significant power consumption benefits to be realised. However, as the difference between the peripheral voltage supply and the cell voltage supply becomes larger, this can significantly adversely reduce the effect of the write assist mechanism due to that write assist mechanism operating from the peripheral voltage supply. As a particular example, considering a capacitive based negative bitline boost mechanism, the capacitive boost is dependent on the peripheral voltage supply, and accordingly as the peripheral voltage supply is reduced, the amount of the boosting effect is reduced. This can lead to a significant reduction in the writeability of the memory cells even in memory devices that incorporate write assist mechanisms. Accordingly, it would be desirable to improve the writeability of memory cells.